In the first step, we extract the timing and clock information from the design. The required information differs between LP-based and GNN-based FF clustering based on their inputs. In 2D design, we extract the necessary information directly from the design after the CTS stage, with the estimated routing information obtained from the global routing. In 3D, the clock tree has been built in the CTS stage of S2D’s Pseudo-3D [3]. However, we only obtain 3D placement after the tier partitioning stage, which only contains cell information such as FFs, clock buffers, and combinational logic cells but not routing. Therefore, we perform full-chip routing to extract the clock tree and timing information. The full-chip routing combines the top and bottom dies into a single design using a 3D Back-End-Of-Line with a double metal stack, as in the “Initial 3D Placement” and “Initial 3D routing” stages in Figure 2. As a result, both top and bottom cells are overlapped, but their pins are of different metal layers. The top cells have pins at the top metal layer, while the bottom cells have pins at the bottom. After that, we perform the global and detailed routing, including both the clock and signal nets, with a fixed cell placement. Once the routing is completed, we extract the necessary information from the fully routed 3D design using the Cadence Innovus tool.
GNN-based Multi-bit Flip-flop Clustering and Post-clustering Design Optimization for Energy-efficient 3D ICs
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In high-performance three-dimensional Integrated Circuits (3D ICs), clock networks consume a large portion of the full-chip power. However, no previous 3D IC work has ever optimized 3D clock networks for both power and performance simultaneously, which results in sub-optimal 3D designs. To overcome this issue, in this article, we propose a GNN-based flip-flop clustering algorithm that merges single-bit flip-flops into multi-bit flip-flops in an unsupervised manner, which jointly optimizes the power and performance metrics of clock networks. Moreover, we integrate our algorithm into the state-of-the-art 3D physical design flow and verify the integration, which leads to a better 3D full-chip design. Experimental results on eight industrial benchmarks demonstrate that the algorithm achieves improvements up to 18% in total power and 8.2% in performance over the state-of-the-art 3D flow.
1 INTRODUCTION
Due to the lack of commercial three-dimensional (3D) physical design tools, existing 3D Integrated Circuits (IC) implementation flows leverage pseudo-3D approaches [1] to build commercial-quality 3D ICs from 2D commercial tools. Mainly, these 3D flows rely on 2D tools to perform pseudo-3D placement and routing on projected 2D layouts. To improve the power consumption of the final full-chip design, existing 3D flows merely focus on improving the switching power, given that it can be straightforwardly achieved through wirelength reduction. However, the clock and the internal cell power, which constitute a significant portion of the total power [2], need to be optimized directly in the existing 3D design flows. In addition, due to the inferiority of the tier partitioning algorithm named bin-based min-cut algorithm, which most of the previous works [3] adopt, severe timing degradation often appears in the final 3D full-chip designs due to the ill-decided locations of registers. Therefore, a methodology that jointly improves the power and performance of 3D ICs is urgently needed in this work.
Generally speaking, 3D design flows can be categorized into two categories: partitioning-first and partitioning-last. Previous work [4], a partitioning-last design flow [1], has proposed a partition mitigation strategy to improve the power and performance of 3D ICs by partitioning clock buffers and flip-flops (FFs) based on a clock tree hierarchy while moving cells on critical paths within clusters to prevent skew degradation. However, this heuristic algorithm requires parameter tuning for each design benchmark and only shows marginal improvements after long tuning iterations. In partitioning-first design flow, previous work [5] attempted to resolve the timing degradation by enhancing placement constraints. Despite the performance improvement, the clock and sequential power still need to be fully optimized to have more power saving than the 2D ICs counterparts.
The clock and sequential power have lately become essential factors in the total power due to the high clock frequency in the gigahertz range. A clock delivery network consists of a source and multiple sinks (=FFs) [6]. The source is distributed from the center of the footprint with buffers and inverters in the tree structure and, last, to the leaf nodes. Different types of FFs are designed to support many functionalities, and their power estimations differ [7]. Therefore, the algorithm to co-optimize the clock delivery network for timing and power is mandatory in 2D and 3D design.
In this article, we propose joint power and timing optimization for 3D ICs through FF clustering. Merging single-bit FFs to multi-bit flip-flops (MBFF) is well known to help optimize clock power and timing in 2D designs [8], which has become a must-use technique in industrial design flows. MBFF provides power saving by sharing the same clock buffers with multiple sets of master–slave latches. However, there exist a few drawbacks in existing 2D MBFF algorithms. By focusing only on an arrival time constraint, another FF clustering approach [9] becomes applicable to industrial designs, because the arrival time is not coupled between FFs. However, this clustering approach only optimizes the clock network locally, because it only clusters neighboring flops whose arrival constraints are not violated, severely limiting the total number of FFs available to be clustered. Nonetheless, the most severe drawback of previous works [8, 9] is that after flop clustering, the underlying placement is not accordingly improved with the new locations of flops. They rely on the subsequent routing stages and optimizations to resolve the violations.
In this work, we advance the traditional MBFF algorithms through machine learning. Furthermore, we develop a novel learning-based flop clustering framework that improves both 2D and 3D ICs by jointly optimizing the performance and power metrics. Specifically, we propose a novel clock network optimization technique called Multi-bit FF clustering (MBFC) that can be integrated with any design implementation flow. Our approach is elegantly based on graph neural networks (GNNs) and essential features that learn to find good clustering results by understanding netlist characteristics. The main contributions of this work are listed as follows:
We extend the state-of-the-art 3D design flows with the ability to perform effective FF clustering to improve 3D QoR metrics.
We propose a novel GNN-based approach with essential features to cluster the clock cells from similarities instead of the traditional clustering algorithm.
We further analyzed and quantified the impact of each feature on the final clustering results.
The GNN-based flip-flop clustering algorithm reduces parameter tuning efforts in a practical runtime.
Our framework improves the final 3D full-chip design using an efficient multi-bit flip-flop clustering algorithm. Additionally, the framework also supports the 2D IC design flow.
Experimental results demonstrate that our proposed algorithm outperforms the existing 3D state-of-the-art flows with up to 18% and 8.2% improvements in the total power and performance, respectively.
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alert state history “flip flop” effect #17591
cicciopizza opened this issue Jun 14, 2019 · 7 comments
cicciopizza opened this issue Jun 14, 2019 · 7 comments
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cicciopizza commented Jun 14, 2019
What happened:
I have a data series on influxDB that returns all values = 0
I configured a simple Alert: when avg() query A last 5m is below 50 > Alert
And I configured: If no data or all values are null > No Data (default configuration)
The rule is evaluated every 5 sec.
if I repeatedly click on test rule, the result is ALWAYS the expected one: Alerting:
But if I look in “State History” I see a “flip flop” between: Alert and “No data”:
IMPORTANT .
Using graphana v5.3.4 (69630b9) on the same server and same datasource, it works correctly . 
What you expected to happen:
The same behavior of graphana v5.3.4
How to reproduce it (as minimally and precisely as possible):
I have already written above how to reproduce the problem:
a series of data at 0 (but I have the same effect even when there are different data)
The problem seems to be the configuration of the parameter;
If no data or all values are null > No Data
Anything else we need to know?:
Environment:
- Grafana version: 6.2.2
- Data source type & version: influxdb 1.7.6
- OS Grafana is installed on: ubuntu 18.04
- User OS & Browser: Chrome
- Grafana plugins: Native Panel Graph
- Others:
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